| stack = dst * src |
> "ae 3,4,*" 0xc > "ae 5,5,*" 0x19 |
| / |
src,dst |
DIV |
stack = dst / src |
> "ae 2,4,/" 0x2 > "ae 5,5,/" 0x1 > "ae 5,9,/" 0x1 |
| % |
src,dst |
MOD |
stack = dst % src |
> "ae 2,4,%" 0x0 > "ae 5,5,%" 0x0 > "ae 5,9,%" 0x4 |
| ~ |
bits,src |
SIGNEXT |
stack = src sign extended |
> "ae 8,0x80,~" 0xffffffffffffff80 |
| ~/ |
src,dst |
SIGNED DIV |
stack = dst / src (signed) |
> "ae 2,-4,~/" 0xfffffffffffffffe |
| ~% |
src,dst |
SIGNED MOD |
stack = dst % src (signed) |
> "ae 2,-5,~%" 0xffffffffffffffff |
| ! |
src |
NEG |
stack = !!!src |
> "ae 1,!" 0x0 > "ae 4,!" 0x0 > "ae 0,!" 0x1 |
| ++ |
src |
INC |
stack = src++ |
> ar r_00=0;ar r_00 0x00000000 > "ae r_00,++" 0x1 > ar r_00 0x00000000 > "ae 1,++" 0x2 |
| -- |
src |
DEC |
stack = src-- |
> ar r_00=5;ar r_00 0x00000005> "ae r_00,--" 0x4 > ar r_00 0x00000005 > "ae 5,--" 0x4 |
| = |
src,reg |
EQU |
reg = src |
> "ae 3,r_00,=" > aer r_00 0x00000003 > "ae r_00,r_01,=" > aer r_01 0x00000003 |
| := |
src,reg |
weak EQU |
reg = src without side effects |
> "ae 3,r_00,:=" > aer r_00 0x00000003 > "ae r_00,r_01,:=" > aer r_01 0x00000003 |
| += |
src,reg |
ADD eq |
reg = reg + src |
> ar r_01=5;ar r_00=0;ar r_00 0x00000000 > "ae r_01,r_00,+=" > ar r_00 0x00000005 > "ae 5,r_00,+=" > ar r_00 0x0000000a |
| -= |
src,reg |
SUB eq |
reg = reg - src |
> "ae r_01,r_00,-=" > ar r_00 0x00000004 > "ae 3,r_00,-=" > ar r_00 0x00000001 |
| *= |
src,reg |
MUL eq |
reg = reg * src |
> ar r_01=3;ar r_00=5;ar r_00 0x00000005> "ae r_01,r_00,*=" > ar r_00 0x0000000f > "ae 2,r_00,*=" > ar r_00 0x0000001e |
| /= |
src,reg |
DIV eq |
reg = reg / src |
> ar r_01=3;ar r_00=6;ar r_00 0x00000006 > "ae r_01,r_00,/=" > ar r_00 0x00000002 > "ae 1,r_00,/=" > ar r_00 0x00000002 |
| %= |
src,reg |
MOD eq |
reg = reg % src |
> ar r_01=3;ar r_00=7;ar r_00 0x00000007 > "ae r_01,r_00,%=" > ar r_00 0x00000001 > ar r_00=9;ar r_00 0x00000009 > "ae 5,r_00,%=" > ar r_00 0x00000004 |
| <<= |
src,reg |
Shift Left eq |
reg = reg << src |
> ar r_00=1;ar r_01=1;ar r_01 0x00000001 > "ae r_00,r_01,<<=" > ar r_01 0x00000002 > "ae 2,r_01,<<=" > ar r_010x00000008 |
| >>= |
src,reg |
Shift Right eq |
reg = reg << src |
> ar r_00=1;ar r_01=8;ar r_01 0x00000008 > "ae r_00,r_01,>>=" > ar r_01 0x00000004 > "ae 2,r_01,>>=" > ar r_01 0x00000001 |
| &= |
src,reg |
AND eq |
reg = reg & src |
> ar r_00=2;ar r_01=6;ar r_01 0x00000006 > "ae r_00,r_01,&=" > ar r_01 0x00000002 > "ae 2,r_01,&=" > ar r_01 0x00000002 > "ae 1,r_01,&=" > ar r_01 0x00000000 |
| |= |
src,reg |
OR eq |
reg = reg | src |
> ar r_00=2;ar r_01=1;ar r_01 0x00000001 > "ae r_00,r_01,|=" > ar r_01 0x00000003 > "ae 4,r_01,|=" > ar r_01 0x00000007 |
| ^= |
src,reg |
XOR eq |
reg = reg ^ src |
> ar r_00=2;ar r_01=0xab;ar r_01 0x000000ab > "ae r_00,r_01,^=" > ar r_01 0x000000a9 > "ae 2,r_01,^=" > ar r_01 0x000000ab |
| ++= |
reg |
INC eq |
reg = reg + 1 |
> ar r_00=4;ar r_00 0x00000004 > "ae r_00,++=" > ar r_00 0x00000005 |
| --= |
reg |
DEC eq |
reg = reg - 1 |
> ar r_00=4;ar r_00 0x00000004 > "ae r_00,--=" > ar r_00 0x00000003 |
| != |
reg |
NOT eq |
reg = !reg |
> ar r_00=4;ar r_00 0x00000004 > "ae r_00,!=" > ar r_00 0x00000000 > "ae r_00,!=" > ar r_00 0x00000001 |
| --- |
--- |
--- |
--- |
---------------------------------------------- |
| =[] =[*] =[1] =[2] =[4] =[8] |
src,dst |
poke |
*dst=src |
> "ae 0xdeadbeef,0x10000,=[4]," > pxw 4@0x10000 0x00010000 0xdeadbeef .... > "ae 0x0,0x10000,=[4]," > pxw 4@0x10000 0x00010000 0x00000000 |
| [] [*] [1] [2] [4] [8] |
src |
peek |
stack=*src |
> w test@0x10000 > "ae 0x10000,[4]," 0x74736574 > ar r_00=0x10000 > "ae r_00,[4]," 0x74736574 |
| |=[] |=[1] |=[2] |=[4] |=[8] |
reg |
nombre |
code |
> > |
| SWAP |
|
Swap |
Swap two top elements |
SWAP |
| DUP |
|
Duplicate |
Duplicate top element in stack |
DUP |
| NUM |
|
Numeric |
If top element is a reference (register name, label, etc), dereference it and push its real value |
NUM |
| CLEAR |
|
Clear |
Clear stack |
CLEAR |
| BREAK |
|
Break |
Stops ESIL emulation |
BREAK |
| GOTO |
n |
Goto |
Jumps to Nth ESIL word |
GOTO 5 |
| TODO |
|
To Do |
Stops execution (reason: ESIL expression not completed) |
TODO |